The present invention relates to field programmable gate arrays (FPGAs) generally, and more particularly to selectively disabling the reading of output of configuration and/or internal data from an FPGA.
Field programmable gate array devices are logic or mixed signal devices that may be configured to provide desirable user-defined functions. FPGAs are typically configured by receiving configuration data from a configuration device. This configuration data may be referred to as a configuration bitstream or program object file (POF). The configuration bitstream opens and closes switches formed on an FPGA such that a desired electrical configuration is achieved.
Modern FPGAs contain hundreds of thousands of logic gates, as well as processors, memories, dedicated analog function blocks, and other circuits. This extensive circuitry requires a correspondingly long configuration bitstream to configure it. For example, 55 Megabits of configuration data are now needed by some FPGAs.
This configuration data represents an FPGA user design that is the outcome of a huge investment in manpower and research and development costs, often in the million dollar range. To protect this investment, it would be beneficial to prevent reading out of the configuration data, as well as any internal data, particularly internal data that may give away the configuration data.
However, it can be beneficial in error correction during field use, as well as during design debugging, for an end user to have access to the data on an FPGA. In some applications where the error correction is critical, some FPGA designers and manufacturers are willing to forego security concerns, such as in the medical field, aerospace, and telecommunications.
Thus, what is needed are circuits, methods, and apparatus that selectively determine a setting for the allowance of access to certain data while preventing the end user from altering this setting. Additionally, it would be beneficial for the selection to be easily implemented, cost effective, and secure.